1. Field of the Invention
This invention generally relates to a semiconductor device and to a control method for a semiconductor device.
2. Description of the Related Art
In recent years, applications of non-volatile semiconductor memories such as flash memories or the like have remarkably expanded. Flash memories are known which employ a cell array architecture such as NOR type flash memories, NAND type flash memories, AND type flash memories, and the like. One of the characteristic aspects of flash memories is an erase operation which operates on a sector basis. Various proposals have been made for the sector arrangement. For example, it is well known that sectors are located in a matrix, the sectors laterally connected by a global word line and vertically connected by a vertical word line. Each sector includes multiple local word lines selectively connected via the global word line and the vertical word line.
FIG. 1 is a view showing the main circuit components to be used when a high voltage is applied to a local word line decoder (word line driver) in a conventional flash memory as disclosed in U.S. Pat. No. 6,646,950 (“Patent Document 1”). As shown in FIG. 1, a flash memory 1 includes a high voltage generating circuit 2, switch circuits 3 provided for respective banks, a high voltage output circuit (vpxv) 4, high voltage output circuits (gvpx) 5 provided for respective sectors, global word line decoders (xdec) 6, a vertical word line decoder (vxdec) 7, and local word line decoders (xdec_sub) 8. The local word line decoders (xdec_sub) 8 drive the word line by using a bootstrap as disclosed in more detail below. The high voltage generating circuit 2 generates the word line voltage (RVPXG) and the word line driving voltage (GVPXG).
FIG. 2 is a circuit diagram showing the structure of a local word line decoder (xdec_sub) 8 as disclosed in Patent Document 1. As shown in FIG. 2, the local word line decoder (xdec_sub) 8 is composed of n-channel transistors M1, M2, and M3. The transistor M1 is a pull-up transistor, and the transistor M2 is a pull-down transistor.
A vertical word line VWL is selectively connected to a local word line P2WL(n) via the transistor M1. The gate of the transistor M1 is controlled by a global word line GWLN via the transistor M3. The high voltage generating circuit 2 is employed as a single voltage source, and the word line voltage applied to the vertical word line VWL and the word line driving voltage applied to the global word line GWLN have the same potential levels. The local word line P2WL and the vertical word line VWL are configured to have the same potentials by coupling a node BST (Bootstrap) and the vertical word line VWL and pulling up to a higher level.
The following problems arise, however, when the local word line decoder (xdec_sub) 8 is driven by only a single voltage source as described above. Firstly, as the flash memories are further downsized, there is a demand for downsizing the above-mentioned transistors included in the local word line decoder as much as possible. Such demand reduces a capacitance CB between the node BST and the vertical word line VWL, making the Bootstrap hard to adequately operate in that a sufficient gate voltage is not available for the gate voltage of the transistor M1.
Secondly, while the word line is being driven for a long period, the node BST is discharged by the leakage from the transistor M3 that cramps the node BST, thereby reducing the voltage in the node BST. Accordingly, a sufficient voltage is not available for a gate voltage of the transistor M1 resulting in a voltage drop in the word line. Thirdly, as the flash memories are further downsized, the channel length of the transistor is also shortened. The leakage from the transistor M3 becomes greater and poses a problem, even if the word line is driven for a short period. The above-described problems create limitations in downsizing the transistor included in the word line driver.